IEEE PROJECTS LIST - YEAR OF 2019-2020


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VLSI DESIGNS \ VLSI DESIGN \ CMOS
Code Project Title
IESVL-0071 28-Nm Latch-Type Sense Amplifier Modification For Coupling Suppression
  
 
IESVL-0086 A Modified Partial Product Generator For Redundant Binary Multipliers
  
 
IESVL-0068 Approximate Error Detection With Stochastic Checkers
  
 
IESVL-0091 Area-Time Efficient Architecture Of Fft-Based Montgomery Multiplication
  
 
IESVL-0130 Design A Novel Sram Architecture Using Sleepy Stack Technique
  
 
IESVL-0088 Design And Synthesis Of Combinational Circuits Using Reversible Decoder In Xilinx
  
 
IESVL-0132 Design Of 12-Bit Digital To Analog Converter Using Cmos
  
 
IESVL-0134 Design Of Low Power High Speed Sram Architecture Using Sleepy Stack Approach
  
 
IESVL-0059 Dual-Quality 4:2 Compressors For Utilizing In Dynamic Accuracy Configurable Multipliers
  
 
IESVL-0070 Energy-Efficient Vlsi Realization Of Binary 64 Division With Redundant Number Systems
  
 
IESVL-0090 High-Speed And Energy-Efficient Carry Skip Adder Operating Under A Wide Range Of Supply Voltage Levels
  
 
IESVL-0073 Majority-Logic-Optimized Parallel Prefix Carry Look-Ahead Adder Families Using Adiabatic Quantum-Flux-Parametron Logic
  
 
IESVL-0072 Power-Gated 9T Sram Cell For Low-Energy Operation
  
 
IESVL-0092 Probability-Driven Multibit Flip-Flop Integration With Clock Gating
  
 
IESVL-0069 Reconfigurable Constant Multiplication For Fpgas
  
IESVL-0087 Reliability Enhancement Of Low-Power Sequential Circuits Using Reconfigurable Pulsed Latches
  
 
IESVL-0067 Soft Error Rate Reduction Of Combinational Circuits Using Gate Sizing In The Presence Of Process Variations
  
 
IESVL-0136 Ultra Low-Voltage High Speed Schmitt Trigger Cmos Circuit
  
 
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